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DSpace at IIT Bombay >
Browsing by Author RAMGOPAL RAO, V
Showing results 20 to 39 of 70
| Issue Date | Title | Author(s) | | 2001 | Effect of fringing capacitances in sub 100 nm MOSFETs with high-K gate dielectrics | MOHAPATRA, NR; DUTTA, A; DESAI, MP; RAMGOPAL RAO, V |
| 2002 | The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance | DESAI, MP; MOHAPATRA, NR; NARENDRA, SG; RAMGOPAL RAO, V |
| 2004 | The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance | DESAI, MP; NARASIMHULU, K; NARENDRA, SG; RAMGOPAL RAO, V |
| 2003 | Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs | MOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V; SHUKURI, S; BUDE, JD |
| 2006 | The effects of varying tilt angle of halo implant on the performance of sub 100nm LAC MOSFETs | SARKAR, P; MALLIK, A; SARKAR, CK; RAMGOPAL RAO, V |
| 2005 | Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs | PATIL, MB; VINAY KUMAR, D; NARASIMHULU, K; REDDY, PS; BAGHINI, MS; SHARMA, DK; RAMGOPAL RAO, V |
| 2009 | Fabrication and characterization of a polymeric microcantilever with an encapsulated hotwire CVD polysilicon piezoresistor | KALE, NS; NAG, S; PINTO, RICHARD; RAMGOPAL RAO, V |
| 2005 | Forward body-biased single halo MOS devices for low voltage analog circuits | NARASIMHULU, K; RAMGOPAL RAO, V |
| 1997 | High-field stressing of LPCVD gate oxides | RAMGOPAL RAO, V; EISELE, I; PATRIKAR, RM; SHARMA, DK; GRABOLLA, T; VASI, J |
| 2003 | Highly conducting doped poly-Si deposited by hot wire CVD and its applicability as gate material for CMOS devices | PATIL, SAMADHAN B; VAIRAGAR, ANAND V; KUMBHAR, ALKA A; SAHU, LAXMI; RAMGOPAL RAO, V; VENKATRAMANI, N; DUSANE, RO; SCHROEDER, B |
| 1999 | Hot-carrier induced interface degradation in jet vapor deposited SiN MNSFETs as studied by a novel charge pumping technique | MAHAPATRA, S; RAMGOPAL RAO, V; PARIKH, CD; VASI, J; CHENG, B; KHARE, M; WOO, JCS |
| 2003 | The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMs | MOHAPATRA, NR; NAIR, DR; MAHAPATRA, S; RAMGOPAL RAO, V; SHUKURI, S |
| 2003 | Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance | SHARMA, DK; NARASIMHULU, K; RAMGOPAL RAO, V |
| 1999 | Low temperature-high pressure grown thin gate dielectrics for MOS applications | RAMGOPAL RAO, V; MAHAPATRA, S; SHARMA, DK; VASI, J; GRABOLLA, T; EISELE, I; HANSCH, W |
| 2005 | A meso-pyridyl porphyrin self-assembled monolayer on gold substrates for molecular electronics applications | SATHYAPALAN, AMARCHAND; LOHANI, ANUP; SANTRA, SANGITA; RAVIKANTH, M; MUKHERJI, SOUMYO; RAMGOPAL RAO, V |
| 2008 | Metallated porphyrin self assembled monolayers as Cu diffusion barriers for the nano-sale CMOS technologies | KHADERBAD, MA; NAYAK, K; YEDUKONDALU, M; RAVIKANTH, M; MUKHERJI, SOUMYA; RAMGOPAL RAO, V |
| 2005 | NBTI degradation and its impact for analog circuit reliability | RAMGOPAL RAO, V; JHA, NEERAJ K; REDDY, PS; SHARMA, DK |
| 1996 | Neutral electron trap generation under irradiation in reoxidized nitrided gate dielectrics | RAMGOPAL RAO, V; SHARMA, DK; VASI, J |
| 2005 | A new drain voltage enhanced NBTI degradation mechanism | JHA, NEERAJ K; REDDY, PS; RAMGOPAL RAO, V |
| 2003 | A new method to characterize border traps in submicron transistors using hysteresis in the drain current | RAMGOPAL RAO, V; MANJULA RANI, KN; VASI, J |
Showing results 20 to 39 of 70
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