|
|
DSpace at IIT Bombay >
Browsing by Author RAMGOPAL RAO, V
Showing results 7 to 26 of 70
| Issue Date | Title | Author(s) | | 2007 | Border-trap characterization in high-κ strained-Si MOSFETs | MAJI, DEBABRATA; DUTTAGUPTA, SP; RAMGOPAL RAO, V; YEO, CHIA CHING; CHO, BYUNG-JIN |
| 1999 | Capacitance degradation due to fringing field in deep sub-micron MOSFETs with High-K gate dielectrics | INANI, A; RAMGOPAL RAO, V; CHENG, B; ZEITZOFF, P; WOO, JCS |
| 1999 | Channel engineering for high speed sub-1.0 V power supply deep sub-micron CMOS | CHENG, BAOHONG; INANI, ANAND; RAMGOPAL RAO, V; WOO, JCS |
| 2001 | Characterization of lateral asymmetric channel (LAC) thin film SOI MOSFETs | NAJEEB-UD-DIN HAKIM; DUNGA, MV; AATISH KUMAR; RAMGOPAL RAO, V; VASI, J |
| 1998 | Charge injection using gate-induced-drain-leakage current for characterization of plasma edge damage in CMOS devices | BROZEK, T; RAMGOPAL RAO, V; SRIDHARAN, A; WERKING, JD; CHAN, YD; VISWANATHAN, CR |
| 2003 | CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters | MAHAPATRA, S; MOHAPATRA, NR; NAIR, DR; RAMGOPAL RAO, V; SHUKURI, S; BUDE, JD |
| 2000 | A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique | MAHAPATRA, S; PARIKH, CD; RAMGOPAL RAO, V; VISWANATHAN, CR; VASI, J |
| 2003 | Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics | MOHAPATRA, NR; DESAI, MP; RAMGOPAL RAO, V |
| 2007 | Device optimization of bulk FinFETs and its comparison with SOI FinFETs | MANOJ, CR; MEENAKSHI, N; DHANYA, V; RAMGOPAL RAO, V |
| 2000 | Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs | MAHAPATRA, S; PARIKH, CD; RAMGOPAL RAO, V; VISWANATHAN, CR; VASI, J |
| 1999 | A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETs | MAHAPATRA, S; PARIKH, CD; VASI, J; RAMGOPAL RAO, V; VISWANATHAN, CR |
| 2000 | Drain bias dependence of gate oxide reliability in conventional and asymmetrical channel MOSFETs in the low voltage regime | ANIL, KG; MAHAPATRA, S; EISELE, I; RAMGOPAL RAO, V; VASI, J |
| 2008 | Drain current model including velocity saturation for symmetric double-gate MOSFETs | VENKATNARAYAN, HARIHARAN; VASI, J; RAMGOPAL RAO, V |
| 2001 | Effect of fringing capacitances in sub 100 nm MOSFETs with high-K gate dielectrics | MOHAPATRA, NR; DUTTA, A; DESAI, MP; RAMGOPAL RAO, V |
| 2002 | The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance | DESAI, MP; MOHAPATRA, NR; NARENDRA, SG; RAMGOPAL RAO, V |
| 2004 | The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance | DESAI, MP; NARASIMHULU, K; NARENDRA, SG; RAMGOPAL RAO, V |
| 2003 | Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs | MOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V; SHUKURI, S; BUDE, JD |
| 2006 | The effects of varying tilt angle of halo implant on the performance of sub 100nm LAC MOSFETs | SARKAR, P; MALLIK, A; SARKAR, CK; RAMGOPAL RAO, V |
| 2005 | Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs | PATIL, MB; VINAY KUMAR, D; NARASIMHULU, K; REDDY, PS; BAGHINI, MS; SHARMA, DK; RAMGOPAL RAO, V |
| 2009 | Fabrication and characterization of a polymeric microcantilever with an encapsulated hotwire CVD polysilicon piezoresistor | KALE, NS; NAG, S; PINTO, RICHARD; RAMGOPAL RAO, V |
Showing results 7 to 26 of 70
|
