Browsing by Author RAMGOPAL RAO, V

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Issue DateTitleAuthor(s)
2003Application of look-up table approach to high-K gate dielectric MOS transistor circuitsVINAY KUMAR, D; MOHAPATRA, NR; PATIL, MB; RAMGOPAL RAO, V
2007Border-trap characterization in high-κ strained-Si MOSFETsMAJI, DEBABRATA; DUTTAGUPTA, SP; RAMGOPAL RAO, V; YEO, CHIA CHING; CHO, BYUNG-JIN
1999Capacitance degradation due to fringing field in deep sub-micron MOSFETs with High-K gate dielectricsINANI, A; RAMGOPAL RAO, V; CHENG, B; ZEITZOFF, P; WOO, JCS
1999Channel engineering for high speed sub-1.0 V power supply deep sub-micron CMOSCHENG, BAOHONG; INANI, ANAND; RAMGOPAL RAO, V; WOO, JCS
2001Characterization of lateral asymmetric channel (LAC) thin film SOI MOSFETsNAJEEB-UD-DIN HAKIM; DUNGA, MV; AATISH KUMAR; RAMGOPAL RAO, V; VASI, J
1998Charge injection using gate-induced-drain-leakage current for characterization of plasma edge damage in CMOS devicesBROZEK, T; RAMGOPAL RAO, V; SRIDHARAN, A; WERKING, JD; CHAN, YD; VISWANATHAN, CR
2003CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parametersMAHAPATRA, S; MOHAPATRA, NR; NAIR, DR; RAMGOPAL RAO, V; SHUKURI, S; BUDE, JD
2000A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping techniqueMAHAPATRA, S; PARIKH, CD; RAMGOPAL RAO, V; VISWANATHAN, CR; VASI, J
2003Detailed analysis of FIBL in MOS transistors with high-k gate dielectricsMOHAPATRA, NR; DESAI, MP; RAMGOPAL RAO, V
2007Device optimization of bulk FinFETs and its comparison with SOI FinFETsMANOJ, CR; MEENAKSHI, N; DHANYA, V; RAMGOPAL RAO, V
2000Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETsMAHAPATRA, S; PARIKH, CD; RAMGOPAL RAO, V; VISWANATHAN, CR; VASI, J
1999A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETsMAHAPATRA, S; PARIKH, CD; VASI, J; RAMGOPAL RAO, V; VISWANATHAN, CR
2000Drain bias dependence of gate oxide reliability in conventional and asymmetrical channel MOSFETs in the low voltage regimeANIL, KG; MAHAPATRA, S; EISELE, I; RAMGOPAL RAO, V; VASI, J
2008Drain current model including velocity saturation for symmetric double-gate MOSFETsVENKATNARAYAN, HARIHARAN; VASI, J; RAMGOPAL RAO, V
2001Effect of fringing capacitances in sub 100 nm MOSFETs with high-K gate dielectricsMOHAPATRA, NR; DUTTA, A; DESAI, MP; RAMGOPAL RAO, V
2002The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performanceDESAI, MP; MOHAPATRA, NR; NARENDRA, SG; RAMGOPAL RAO, V
2004The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performanceDESAI, MP; NARASIMHULU, K; NARENDRA, SG; RAMGOPAL RAO, V
2003Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMsMOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V; SHUKURI, S; BUDE, JD
2006The effects of varying tilt angle of halo implant on the performance of sub 100nm LAC MOSFETsSARKAR, P; MALLIK, A; SARKAR, CK; RAMGOPAL RAO, V
2005Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETsPATIL, MB; VINAY KUMAR, D; NARASIMHULU, K; REDDY, PS; BAGHINI, MS; SHARMA, DK; RAMGOPAL RAO, V