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Browsing by Author RAMGOPAL RAO, V

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Issue DateTitleAuthor(s)
2000Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETsMAHAPATRA, S; PARIKH, CD; RAMGOPAL RAO, V; VISWANATHAN, CR; VASI, J
1999A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETsMAHAPATRA, S; PARIKH, CD; VASI, J; RAMGOPAL RAO, V; VISWANATHAN, CR
2000Drain bias dependence of gate oxide reliability in conventional and asymmetrical channel MOSFETs in the low voltage regimeANIL, KG; MAHAPATRA, S; EISELE, I; RAMGOPAL RAO, V; VASI, J
2008Drain current model including velocity saturation for symmetric double-gate MOSFETsVENKATNARAYAN, HARIHARAN; VASI, J; RAMGOPAL RAO, V
2001Effect of fringing capacitances in sub 100 nm MOSFETs with high-K gate dielectricsMOHAPATRA, NR; DUTTA, A; DESAI, MP; RAMGOPAL RAO, V
2002The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performanceDESAI, MP; MOHAPATRA, NR; NARENDRA, SG; RAMGOPAL RAO, V
2004The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performanceDESAI, MP; NARASIMHULU, K; NARENDRA, SG; RAMGOPAL RAO, V
2003Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMsMOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V; SHUKURI, S; BUDE, JD
2006The effects of varying tilt angle of halo implant on the performance of sub 100nm LAC MOSFETsSARKAR, P; MALLIK, A; SARKAR, CK; RAMGOPAL RAO, V
2005Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETsPATIL, MB; VINAY KUMAR, D; NARASIMHULU, K; REDDY, PS; BAGHINI, MS; SHARMA, DK; RAMGOPAL RAO, V
2009Fabrication and characterization of a polymeric microcantilever with an encapsulated hotwire CVD polysilicon piezoresistorKALE, NS; NAG, S; PINTO, RICHARD; RAMGOPAL RAO, V
2005Forward body-biased single halo MOS devices for low voltage analog circuitsNARASIMHULU, K; RAMGOPAL RAO, V
1997High-field stressing of LPCVD gate oxidesRAMGOPAL RAO, V; EISELE, I; PATRIKAR, RM; SHARMA, DK; GRABOLLA, T; VASI, J
2003Highly conducting doped poly-Si deposited by hot wire CVD and its applicability as gate material for CMOS devicesPATIL, SAMADHAN B; VAIRAGAR, ANAND V; KUMBHAR, ALKA A; SAHU, LAXMI; RAMGOPAL RAO, V; VENKATRAMANI, N; DUSANE, RO; SCHROEDER, B
1999Hot-carrier induced interface degradation in jet vapor deposited SiN MNSFETs as studied by a novel charge pumping techniqueMAHAPATRA, S; RAMGOPAL RAO, V; PARIKH, CD; VASI, J; CHENG, B; KHARE, M; WOO, JCS
2003The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMsMOHAPATRA, NR; NAIR, DR; MAHAPATRA, S; RAMGOPAL RAO, V; SHUKURI, S
2003Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performanceSHARMA, DK; NARASIMHULU, K; RAMGOPAL RAO, V
1999Low temperature-high pressure grown thin gate dielectrics for MOS applicationsRAMGOPAL RAO, V; MAHAPATRA, S; SHARMA, DK; VASI, J; GRABOLLA, T; EISELE, I; HANSCH, W
2005A meso-pyridyl porphyrin self-assembled monolayer on gold substrates for molecular electronics applicationsSATHYAPALAN, AMARCHAND; LOHANI, ANUP; SANTRA, SANGITA; RAVIKANTH, M; MUKHERJI, SOUMYO; RAMGOPAL RAO, V
2008Metallated porphyrin self assembled monolayers as Cu diffusion barriers for the nano-sale CMOS technologiesKHADERBAD, MA; NAYAK, K; YEDUKONDALU, M; RAVIKANTH, M; MUKHERJI, SOUMYA; RAMGOPAL RAO, V
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