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DSpace at IIT Bombay >
Browsing by Author RAMGOPAL RAO, V
Showing results 1 to 20 of 70
| Issue Date | Title | Author(s) | | 1999 | 100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric | MAHAPATRA, S; RAMGOPAL RAO, V; MANJULA RANI, KN; PARIKH, CD; VASI, J; CHENG, B; KHARE, M; WOO, JCS |
| 2006 | Analog circuit performance issues with aggressively scaled gate oxide CMOS technologies | NARASIMHULU, K; RAMGOPAL RAO, V |
| 2002 | Analysis of floating body effects in thin film conventional and single pocket SOI MOSFETs using the GIDL current technique | RAMGOPAL RAO, V; NAJEEB-UD-DIN HAKIM; DUNGA, MV; AATISH KUMAR; VASI, J; CHENG, B; WOO, JCS |
| 2001 | Analysis of floating body effects in thin film SOI MOSFETs using the GIDL current technique | DUNGA, MOHAN V; AATISH KUMAR; RAMGOPAL RAO, V |
| 2004 | Anhydrous silanization and antibody immobilization on hotwire CVD deposited silicon oxynitride films | JOSHI, M; SINGH, S; SWAIN, B; PATIL, SAMADHAN B; DUSANE, RO; RAMGOPAL RAO, V; MUKHERJI, SOUMYA |
| 2003 | Application of look-up table approach to high-K gate dielectric MOS transistor circuits | VINAY KUMAR, D; MOHAPATRA, NR; PATIL, MB; RAMGOPAL RAO, V |
| 2007 | Border-trap characterization in high-κ strained-Si MOSFETs | MAJI, DEBABRATA; DUTTAGUPTA, SP; RAMGOPAL RAO, V; YEO, CHIA CHING; CHO, BYUNG-JIN |
| 1999 | Capacitance degradation due to fringing field in deep sub-micron MOSFETs with High-K gate dielectrics | INANI, A; RAMGOPAL RAO, V; CHENG, B; ZEITZOFF, P; WOO, JCS |
| 1999 | Channel engineering for high speed sub-1.0 V power supply deep sub-micron CMOS | CHENG, BAOHONG; INANI, ANAND; RAMGOPAL RAO, V; WOO, JCS |
| 2001 | Characterization of lateral asymmetric channel (LAC) thin film SOI MOSFETs | NAJEEB-UD-DIN HAKIM; DUNGA, MV; AATISH KUMAR; RAMGOPAL RAO, V; VASI, J |
| 1998 | Charge injection using gate-induced-drain-leakage current for characterization of plasma edge damage in CMOS devices | BROZEK, T; RAMGOPAL RAO, V; SRIDHARAN, A; WERKING, JD; CHAN, YD; VISWANATHAN, CR |
| 2003 | CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters | MAHAPATRA, S; MOHAPATRA, NR; NAIR, DR; RAMGOPAL RAO, V; SHUKURI, S; BUDE, JD |
| 2000 | A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique | MAHAPATRA, S; PARIKH, CD; RAMGOPAL RAO, V; VISWANATHAN, CR; VASI, J |
| 2003 | Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics | MOHAPATRA, NR; DESAI, MP; RAMGOPAL RAO, V |
| 2007 | Device optimization of bulk FinFETs and its comparison with SOI FinFETs | MANOJ, CR; MEENAKSHI, N; DHANYA, V; RAMGOPAL RAO, V |
| 2000 | Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs | MAHAPATRA, S; PARIKH, CD; RAMGOPAL RAO, V; VISWANATHAN, CR; VASI, J |
| 1999 | A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETs | MAHAPATRA, S; PARIKH, CD; VASI, J; RAMGOPAL RAO, V; VISWANATHAN, CR |
| 2000 | Drain bias dependence of gate oxide reliability in conventional and asymmetrical channel MOSFETs in the low voltage regime | ANIL, KG; MAHAPATRA, S; EISELE, I; RAMGOPAL RAO, V; VASI, J |
| 2008 | Drain current model including velocity saturation for symmetric double-gate MOSFETs | VENKATNARAYAN, HARIHARAN; VASI, J; RAMGOPAL RAO, V |
| 2001 | Effect of fringing capacitances in sub 100 nm MOSFETs with high-K gate dielectrics | MOHAPATRA, NR; DUTTA, A; DESAI, MP; RAMGOPAL RAO, V |
Showing results 1 to 20 of 70
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