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DSpace at IIT Bombay >
Browsing by Author NARAYANAN, H
Showing results 5 to 24 of 42
| Issue Date | Title | Author(s) | | 1999 | Decomposition of finite state machines for area, delay minimization | SHELAR, RUPESH S; DESAI, MP; NARAYANAN, H |
| 1999 | Efficient DC analysis of RVJ circuits for moment and derivative computations of interconnect networks | BATTERYWALA, SH; NARAYANAN, H |
| 2003 | An efficient practical heuristic for good ratio-cut partitioning | PATKAR, SACHIN; NARAYANAN, H |
| 2009 | Exploiting hybrid analysis in solving electrical networks | SANKAR, VS; NARAYANAN, H; PATKAR, SB |
| 1991 | A FAST ALGORITHM FOR THE PRINCIPAL PARTITION OF A GRAPH | PATKAR, S; NARAYANAN, H |
| 2006 | Fast DC analysis and its application to combinatorial optimization problems | TRIVEDI, GAURAV; DESAI, MP; NARAYANAN, H |
| 2005 | Fast DC analysis and its application to combinatorial optimization problems | TRIVEDI, G; DESAI, MP; NARAYANAN, H |
| 1992 | Fast loop matrix generation for hybrid analysis and a comparison of the sparsity of the loop impedance and MNA impedance submatrices | OVALEKAR, VRINDA S; NARAYANAN, H |
| 2000 | Fast on-line/off-line algorithms for optimal reinforcement of a network and its connections with principal partition | PATKAR, SB; NARAYANAN, H |
| 2003 | Fast on-line/off-line algorithms for optimal reinforcement of a network and its connections with principal partition | PATKAR, SB; NARAYANAN, H |
| 1992 | Fast sequential and randomized parallel algorithms for rigidity and approximate min k-cut | PATKAR, S; NARAYANAN, H |
| 2009 | FPGA based high performance double-precision matrix multiplication | KUMAR, VBY; JOSHI, S; PATKAR, SB; NARAYANAN, H |
| 2010 | FPGA based high performance double-precision matrix multiplication | KUMAR, VBY; JOSHI, S; PATKAR, SB; NARAYANAN, H |
| 2003 | Improving graph partitions using submodular functions | PATKAR, SB; NARAYANAN, H |
| 2002 | Mathematical methods in VLSI | ATRE, MV; SUBRAMANIAN, S; NARAYANAN, H |
| 2004 | Mathematical programming and resistor transformer diode networks | NARAYANAN, H |
| 1978 | MAXIMUM POWER TRANSFER THEOREM | NARAYANAN, H |
| 1991 | A new approach to the problem of PLA partitioning using the theory of the principal lattice of partitions of a submodular function | ROY, SUBIR; NARAYANAN, H |
| 1997 | A new partitioning strategy based on supermodular functions | PATKAR, SACHIN; BATTERYWALA, SH; CHANDRAMOULI, M; NARAYANAN, H |
| 2001 | A note on optimal covering augmentation for graphic polymatroids | PATKAR, SB; NARAYANAN, H |
Showing results 5 to 24 of 42
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