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Browsing by Author MOHAPATRA, NR

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Showing results 1 to 19 of 19
Issue DateTitleAuthor(s)
2003Application of look-up table approach to high-K gate dielectric MOS transistor circuitsVINAY KUMAR, D; MOHAPATRA, NR; PATIL, MB; RAMGOPAL RAO, V
2003CHISEL programming operation of scaled NOR flash EEPROMs - Effect of voltage scaling, device scaling and technological parametersMOHAPATRA, NR; NAIR, DR; MAHAPATRA, S; RAO, VR; SHUKURI, S; BUDE, JD
2003CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parametersMAHAPATRA, S; MOHAPATRA, NR; NAIR, DR; RAMGOPAL RAO, V; SHUKURI, S; BUDE, JD
2002A comparative study of scaling properties of MOS transistors in CHE and CHISEL injection regimeMOHAPATRA, NR; MAHAPATRA, S; RAO, VR
2003Detailed analysis of FIBL in MOS transistors with high-k gate dielectricsMOHAPATRA, NR; DESAI, MP; RAMGOPAL RAO, V
2002Device scaling effects on substrate enhanced degradation in MOS transistorsMOHAPATRA, NR; MAHAPATRA, S; RAO, VR
2002Effective dielectric thickness scaling for high-K gate dielectric MOSFETsBHUWALKA, KK; MOHAPATRA, NR; NARENDRA, SG; RAO, VR
2003The effect of CHE and CHISEL programming operation on drain disturb in flash EEPROMsNAIR, DR; MOHAPATRA, NR; MAHAPATRA, S; SHUKURI, S; BUDE, JD
2001Effect of fringing capacitances in sub 100 nm MOSFETs with high-K gate dielectricsMOHAPATRA, NR; DUTTA, A; DESAI, MP; RAMGOPAL RAO, V
2002The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performanceDESAI, MP; MOHAPATRA, NR; NARENDRA, SG; RAMGOPAL RAO, V
2004Effect of P/E cycling on drain disturb in flash EEPROMs under CHE and CHISEL operationMAHAPATRA, S; NAIR, DR; MOHAPATRA, NR; SHUKURI, S; BUDE, JD
2003Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMsMOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V; SHUKURI, S; BUDE, JD
2002Effect of technology scaling on MOS transistor performance with high-K gate dielectricsMOHAPATRA, NR; DESAI, MP; NARENDRA, SG; RAO, VR
2012Effects of Small Geometries on the Performance of Gate First High-kappa Metal Gate NMOS TransistorsWALKE, AM; MOHAPATRA, NR
2003The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMsMOHAPATRA, NR; NAIR, DR; MAHAPATRA, S; RAMGOPAL RAO, V; SHUKURI, S
2003Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistorsMOHAPATRA, NR; DESAI, MP; NARENDRA, SG; RAO, VR
2002The study of damage generation in n-channel MOS transistors operating in the substrate enhanced gate current regimeMOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V
2001Study of degradation in channel initiated secondary electron injection regimeMOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V
2001Sub-100 nm CMOS circuit performance with high-K gate dielectricsMOHAPATRA, NR; DUTTA, A; SRIDHAR, G; DESAI, MP; RAO, VR
Showing results 1 to 19 of 19

 

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