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DSpace at IIT Bombay >
Browsing by Author MOHAPATRA, NR
Showing results 2 to 18 of 18
| Issue Date | Title | Author(s) | | 2003 | CHISEL programming operation of scaled NOR flash EEPROMs - Effect of voltage scaling, device scaling and technological parameters | MOHAPATRA, NR; NAIR, DR; MAHAPATRA, S; RAO, VR; SHUKURI, S; BUDE, JD |
| 2003 | CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters | MAHAPATRA, S; MOHAPATRA, NR; NAIR, DR; RAMGOPAL RAO, V; SHUKURI, S; BUDE, JD |
| 2002 | A comparative study of scaling properties of MOS transistors in CHE and CHISEL injection regime | MOHAPATRA, NR; MAHAPATRA, S; RAO, VR |
| 2003 | Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics | MOHAPATRA, NR; DESAI, MP; RAMGOPAL RAO, V |
| 2002 | Device scaling effects on substrate enhanced degradation in MOS transistors | MOHAPATRA, NR; MAHAPATRA, S; RAO, VR |
| 2002 | Effective dielectric thickness scaling for high-K gate dielectric MOSFETs | BHUWALKA, KK; MOHAPATRA, NR; NARENDRA, SG; RAO, VR |
| 2003 | The effect of CHE and CHISEL programming operation on drain disturb in flash EEPROMs | NAIR, DR; MOHAPATRA, NR; MAHAPATRA, S; SHUKURI, S; BUDE, JD |
| 2001 | Effect of fringing capacitances in sub 100 nm MOSFETs with high-K gate dielectrics | MOHAPATRA, NR; DUTTA, A; DESAI, MP; RAMGOPAL RAO, V |
| 2002 | The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance | DESAI, MP; MOHAPATRA, NR; NARENDRA, SG; RAMGOPAL RAO, V |
| 2004 | Effect of P/E cycling on drain disturb in flash EEPROMs under CHE and CHISEL operation | MAHAPATRA, S; NAIR, DR; MOHAPATRA, NR; SHUKURI, S; BUDE, JD |
| 2003 | Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs | MOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V; SHUKURI, S; BUDE, JD |
| 2002 | Effect of technology scaling on MOS transistor performance with high-K gate dielectrics | MOHAPATRA, NR; DESAI, MP; NARENDRA, SG; RAO, VR |
| 2003 | The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMs | MOHAPATRA, NR; NAIR, DR; MAHAPATRA, S; RAMGOPAL RAO, V; SHUKURI, S |
| 2003 | Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors | MOHAPATRA, NR; DESAI, MP; NARENDRA, SG; RAO, VR |
| 2002 | The study of damage generation in n-channel MOS transistors operating in the substrate enhanced gate current regime | MOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V |
| 2001 | Study of degradation in channel initiated secondary electron injection regime | MOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V |
| 2001 | Sub-100 nm CMOS circuit performance with high-K gate dielectrics | MOHAPATRA, NR; DUTTA, A; SRIDHAR, G; DESAI, MP; RAO, VR |
Showing results 2 to 18 of 18
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