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DSpace at IIT Bombay >
Browsing by Author MAHAPATRA, S
Showing results 96 to 115 of 138
| Issue Date | Title | Author(s) | | 1985 | ON THE DESIGN OF HIGH-POWER MULTIPLE-ELEMENT LOADED-LINE PHASE SHIFTERS | NAYAGAM, S; MAHAPATRA, S |
| 2005 | On the dispersive versus arrhenius temperature activation of nbti time evolution in plasma nitrided gate oxides: measurements, theory, and implications | VARGHESE, D; SAHA, D; MAHAPATRA, S; AHMED, K; NOURI, F; ALAM, M |
| 2006 | On the generation and recovery of hot carrier induced interface traps: a critical examination of the 2-D R-D model | MAHAPATRA, S; SAHA, D; VARGHESE, D |
| 2006 | On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress | MAHAPATRA, S; SAHA, D; VARGHESE, D; BHARATH KUMAR, P |
| 2010 | On the Nature of Shunt Leakage in Amorphous Silicon p-i-n Solar Cells | DONGAONKAR, S; KARTHIK, Y; WANG, DP; FREI, M; MAHAPATRA, S; ALAM, MA |
| 2007 | On the physical mechanism of NBTI in silicon oxynitride p-MOSFETs: can differences in insulator processing conditions resolve the interface trap generation versus hole trapping controversy? | MAHAPATRA, S; AHMED, K; VARGHESE, D; ISLAM, AE; GUPTA, G; MADHAV, L; SAHA, D; ALAM, MA |
| 2008 | Optimization of gate leakage and NBTI for plasma-nitrided gate oxides by numerical and analytical models | ISLAM, AE; GUPTA, G; AHMED, KZ; MAHAPATRA, S; ALAM, MA |
| 2001 | Performance and hot-carrier reliability of 100 nm channel length jet vapor deposited Si3N4 MNSFETs | MAHAPATRA, S; RAMGOPAL RAO, V; CHENG, B; KHARE, M; PARIKH, CD; WOO, JCS; VASI, J |
| 2009 | Performance and Reliability of Au and Pt Single-Layer Metal Nanocrystal Flash Memory Under NAND (FN/FN) Operation | SINGH, PK; HOFMANN, R; SINGH, KK; KRISHNA, N; MAHAPATRA, S |
| 2002 | Performance and reliability of high density flash EEPROMs under CHISEL programming operation | MAHAPATRA, S; SHUKURI, S; BUDE, JD |
| 2010 | Performance and Reliability Study of Single-Layer and Dual-Layer Platinum Nanocrystal Flash Memory Devices Under NAND Operation | SINGH, PK; BISHT, G; AULUCK, K; SIVATHEJA, M; HOFMANN, R; SINGH, KK; MAHAPATRA, S |
| 1990 | PERFORMANCE EVALUATION OF 2 PASSIVE MMIC COMPONENTS | CHOUDHURY, D; MAHAPATRA, S |
| 2001 | Performance optimization of 60 nm channel length vertical MOSFETs using channel engineering | SHRIVASTAV, G; MAHAPATRA, S; RAMGOPAL RAO, V; VASI, J |
| 2007 | Physical mechanism and gate insulator material dependence of generation and recovery of negative-bias temperature instability in p-MOSFETs | VARGHESE, D; GUPTA, G; LAKKIMSETTI, LM; SAHA, D; AHMED, K; NOURI, F; MAHAPATRA, S |
| 1991 | PIPE ENCLOSED MICROSTRIP TRANSMISSION-LINE | PATIL, KB; MAITI, SK; MAHAPATRA, S |
| 1988 | POWER REDUCTION METHODS FOR NMOS DYNAMIC RANDOM-ACCESS MEMORIES | NAIDU, RV; MAHAPATRA, S |
| 2002 | A predictive reliability model for PMOS bias temperature degradation | MAHAPATRA, S; ALAM, MA |
| 2009 | Recent advances in charge trap flash memories | SANDHYA, C; SINGH, PK; GUPTA, S; ROHRA, H; SHIVATHEJA, M; GANGULY, U; HOFMANN, R; MUKHOPADHYAY, G; MAHAPATRA, S; VASI, J |
| 2007 | Recent issues in negative-bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects, and relaxation | ISLAM, AE; KUFLUOGLU, H; VARGHESE, D; MAHAPATRA, S; ALAM, MA |
| 2009 | Reliability of single and dual layer Pt Nanocrystal devices for NAND flash applications : a 2-region model for endurance defect generation | SINGH, PK; BISHT, G; SIVATHEJA, M; SANDHYA, C; MUKHOPADHYAY, G; MAHAPATRA, S; HOFMANN, R; SINGH, K; KRISHNA, N |
Showing results 96 to 115 of 138
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