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Browsing by Author MAHAPATRA, S

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Issue DateTitleAuthor(s)
2006Lateral profiling of trapped charge in SONOS flash EEPROMs programmed using CHE injectionMAHAPATRA, S; BHARATH KUMAR, P; NAIR, PR; SHARMA, RAVINDER; KAMOHARA, S
1979Least-square collocation as applied to the analysis of strip transmission-linesSESHADRI, TK; MAHAPATRA, S; RAJAIAH, K
1999Low temperature-high pressure grown thin gate dielectrics for MOS applicationsRAMGOPAL RAO, V; MAHAPATRA, S; SHARMA, DK; VASI, J; GRABOLLA, T; EISELE, I; HANSCH, W
1995Mapping of backpropagation learning onto distributed memory multiprocessorsMAHAPATRA, S; MAHAPATRA, RN
1997Mapping of neural network models onto massively parallel hierarchical computer systemsMAHAPATRA, S
2007Material dependence of NBTI physical mechanism in silicon oxynitride (SiON) p-MOSFETs: A comprehensive study by ultra-fast on-the-fly (UF-OTF) I(DLIN) techniqueKUMAR, EN; MAHETA, VD; PURAWAT, S; ISLAM, AE; OLSEN, C; AHMED, K; ALAM, MA; MAHAPATRA, S
2009Material dependence of negative bias temperature instability (NBTI) stress and recovery in SiON p-MOSFETsMAHAPATRA, S; MAHETA, VD; DEORA, S; KUMAR, EN; PURAWAT, S; OLSEN, C; AHMED, K; ISLAM, AE; ALAM, MA
2005Mechanism of drain disturb in SONOS flash EEPROMsBHARATH KUMAR, P; SHARMA, RAVINDER; NAIR, PR; NAIR, DR; KAMOHARA, S; MAHAPATRA, S; VASI, J
2004Mechanism of negative bias temperature instability in CMOS devices: degradation, recovery and impact of nitrogenMAHAPATRA, S; BHARATH KUMAR, P; DALEI, TR; SANA, D; ALAM, MA
2008Metal nanocrystal memory with pt single- and dual-layer NC With low-Leakage AI2O3 Blocking DielectricSINGH, PK; BISHT, G; HOFMANN, R; SINGH, K; KRISHNA, N; MAHAPATRA, S
1980MICROSTRIP TRANSMISSION-LINE ANALYSIS BY THE USE OF THE LEAST-SQUARES COLLOCATION METHODSESHADRI, TK; MAHAPATRA, S; RAJAIAH, K
1988MICROWAVE BEHAVIOR OF ELECTROLESS MICROSTRIP LINES ON SI GAAS SUBSTRATESSINHA, MP; MAHAPATRA, S
2008Mobility degradation due to interface traps in plasma oxynitride PMOS devicesISLAM, AE; MAHETA, VD; DAS, H; MAHAPATRA, S; ALAM, MA
1977MODIFIED ELECTROLESS METHOD FOR FABRICATION OF MICROSTRIP LINES ON ALUMINA SUBSTRATESSESHADRI, TK; MAHAPATRA, S
2001Multi-frequency transconductance technique for interface characterization of deep sub-micron SOI-MOSFETsKUMAR, A; MAHAPATRA, S; LAL, R; RAO, VR
1992MULTILAYERED DIELECTRIC STRIPLINEPATIL, KD; MAITI, SK; MAHAPATRA, S
2004Multi-level programming of NOR flash EEPROMs by CHISEL mechanismNAIR, DR; MAHAPATRA, S; SHUKURI, S; BUDE, JD
2010NBTI lifetime prediction in SiON p-MOSFETs by H/H2 Reaction-Diffusion(RD) and Dispersive hole trapping modelDEORA, S; MAHETA, VD; MAHAPATRA, S
2005Negative bias temperature instability in CMOS devicesMAHAPATRA, S; ALAM, AA; KUMAR, PB; DALEI, TR; VARGHESE, D; SAHA, D
1975New active rc circuit realization of a 3rd-order low-pass butterworth characteristic using grounded capacitors and equal-valued passive elementsNAIMPALLY, SV; MAHAPATRA, S
Showing results 65 to 84 of 138
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