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Browsing by Author MAHAPATRA, S

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Issue DateTitleAuthor(s)
2002Electron-electron interaction signature peak in the substrate current versus gate voltage characteristics of n-channel silicon MOSFETsANIL, KG; MAHAPATRA, S; EISELE, I
2006Endurance and retention characteristics of SONOS EEPROMs operated using BTBT induced hot hole eraseBHARATH KUMAR, P; MURAKAMI, E; KAMOHARA, S; MAHAPATRA, S
2001Experimental verification of the nature of the high energy tail in the electron energy distribution in n-channel MOSFETsANIL, KG; MAHAPATRA, S; EISELE, I
2005Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operationNAIR, DR; MAHAPATRA, S; SHUKURI, S; BUDE, JD
2005Explanation of P/E cycling impact on drain disturb in flash EEPROMs under CHE and CHISEL programming operationMAHAPATRA, S; NAIR, DR; SHUKURI, S; BUDE, JD
1989A FAULT MODEL FOR MULTIVALUED NMOS DYNAMIC RANDOM-ACCESS MEMORIESNAIDU, RV; MAHAPATRA, S
1988FAULT TOLERANCE IN N-MOS RANDOM-ACCESS MEMORIES WITH DYNAMIC REDUNDANCY METHODSNAIDU, RV; MAHAPATRA, S
1990A GAAS DIRECTIONAL COUPLERCHOUDHURY, D; MAHAPATRA, S
2008Gate insulator process dependent NBTI in SiON p-MOSFETsMAHAPATRA, S; MAHETA, VD
2005Hole energy dependent interface trap generation in MOSFET Si/SiO2 interfaceMAHAPATRA, S; VARGHESE, D; ALAM, MA
1999Hot-carrier induced interface degradation in jet vapor deposited SiN MNSFETs as studied by a novel charge pumping techniqueMAHAPATRA, S; RAMGOPAL RAO, V; PARIKH, CD; VASI, J; CHENG, B; KHARE, M; WOO, JCS
2003The impact of channel engineering on the performance reliability and scaling of CHISEL NOR flash EEPROMsMOHAPATRA, NR; NAIR, DR; MAHAPATRA, S; RAMGOPAL RAO, V; SHUKURI, S
2008The impact of gate dielectric nitridation methodology on NBTI of SiON p-MOSFETs as studied by UF-OTF techniqueMAHETA, VD; OLSEN, C; AHMED, K; MAHAPATRA, S
2008The impact of nitrogen engineering in silicon oxynitride gate dielectric on negative-bias temperature instability of p-MOSFETs: A study by ultrafast on-the-fly I-DLIN techniqueMAHETA, VD; OLSEN, C; AHMED, K; MAHAPATRA, S
2009Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under (FN/FN) OperationSANDHYA, C; OAK, AB; CHATTAR, N; JOSHI, AS; GANGULY, U; OLSEN, C; SEUTTER, SM; DATE, L; HUNG, R; VASI, J; MAHAPATRA, S
2005Impact of substrate bias on p-MOSFET negative bias temperature instabilityBHARATH KUMAR, P; DALEI, TR; VARGHESE, D; SAHA, D; MAHAPATRA, S; ALAM, MA
1980IMPROVED ELECTROLESS PROCESS OF COPPER COATING CERAMICS .1. SOME PARAMETERS OF COATING GLASS SUBSTRATESBHATGADDE, LG; MAHAPATRA, S
2009Influence of SiN composition on program and erase characteristics of SANOS-type flash memoriesSANDHYA, C; GANGULY, U; APOORVA, B; OLSEN, C; SEUTTER, S; DATE, L; HUNG, R; VASI, J; MAHAPATRA, S
1987INTEGRAL ANALYSIS OF HYBRID COUPLED SEMICONDUCTOR PHASE SHIFTERSKORI, MH; MAHAPATRA, S
2006Interface-trap driven NBTI for ultrathin (EOT similar to 12A) plasma and thermal nitrided oxynitridesGUPTA, G; MAHAPATRA, S; MADHAV, LL; VARGHESE, D; AHMED, K; NOURI, F
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