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Browsing by Author MAHAPATRA, S

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Issue DateTitleAuthor(s)
2004Cycling endurance of NOR flash EEPROM cells under CHISEL programming operation - impact of technological parameters and scalingNAIR, DR; SHUKURI, S; MAHAPATRA, S
2008Defect generation in p-MOSFETs under negative-bias stress: an experimental perspectiveMAHAPATRA, S; ALAM, MA
2003A detailed experimental investigation of impact ionization in n-channel metal-oxide-semiconductor field-effect-transistors at very low drain voltagesANIL, KG; MAHAPATRA, S; EISELE, I
2014A Detailed Study of Gate Insulator Process Dependence of NBTI Using a Compact ModelJOSHI, K; MUKHOPADHYAY, S; GOEL, N; NANWARE, N; MAHAPATRA, S
2007Development of a 3D simulator for metal Nanocrystal (NC) flash memories under NAND operationNAINANI, A; PALIT, S; SINGH, PK; GANGULY, U; KRISHNA, N; VASI, J; MAHAPATRA, S
2008Development of an ultrafast on-the-fly I DLIN technique to study NBTI in plasma and thermal oxynitride p-MOSFETsMAHETA, VD; NARESH KUMAR, E; PURAWAT, S; OLSEN, C; AHMED, K; MAHAPATRA, S
2000Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETsMAHAPATRA, S; PARIKH, CD; RAMGOPAL RAO, V; VISWANATHAN, CR; VASI, J
2002Device scaling effects on substrate enhanced degradation in MOS transistorsMOHAPATRA, NR; MAHAPATRA, S; RAO, VR
1999A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETsMAHAPATRA, S; PARIKH, CD; VASI, J; RAMGOPAL RAO, V; VISWANATHAN, CR
2000Drain bias dependence of gate oxide reliability in conventional and asymmetrical channel MOSFETs in the low voltage regimeANIL, KG; MAHAPATRA, S; EISELE, I; RAMGOPAL RAO, V; VASI, J
2004Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parametersMAHAPATRA, S; NAIR, DR; SHUKURI, S; BUDE, JD
2007Dual-bit/cell SONOS flash EEPROMs: impact of channel engineering on programming speed and bit coupling effectDATTA, A; BHARATH KUMAR, P; MAHAPATRA, S
2009Dual layer Pt metal nanocrystal flash for multi-level-cell NAND applicationSINGH, PK; BISHT, G; MAHAPATRA, S; HOFMANN, R; SINGH, K
2008The effect of band gap engineering of the nitride storage node on performance and reliability of charge trap flashSANDHYA, C; GANGULY, U; SINGH, KK; OLSEN, C; SEUTTER, SM; CONTI, G; AHMED, K; KRISHNA, N; VASI, J; MAHAPATRA, S
2003The effect of CHE and CHISEL programming operation on drain disturb in flash EEPROMsNAIR, DR; MOHAPATRA, NR; MAHAPATRA, S; SHUKURI, S; BUDE, JD
2004Effect of P/E cycling on drain disturb in flash EEPROMs under CHE and CHISEL operationMAHAPATRA, S; NAIR, DR; MOHAPATRA, NR; SHUKURI, S; BUDE, JD
2003Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMsMOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V; SHUKURI, S; BUDE, JD
2009Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler-Nordheim Tunneling Program/Erase OperationSANDHYA, C; GANGULY, U; CHATTAR, N; OLSEN, C; SEUTTER, SM; DATE, L; HUNG, R; VASI, JA; MAHAPATRA, S
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