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DSpace at IIT Bombay >
Browsing by Author MAHAPATRA, S
Showing results 22 to 41 of 138
| Issue Date | Title | Author(s) | | 2005 | Controlling injected electron and hole profiles for better reliability of split gate SONOS | SRIDHAR, K; BHARATH KUMAR, P; MAHAPATRA, S; MURAKAMI, E; KAMOHARA, S |
| 1980 | CORNER FUNCTION-ANALYSIS OF MICROSTRIP TRANSMISSION-LINES | SESHADRI, TK; MAHAPATRA, S; RAJAIAH, K |
| 2004 | Cycling endurance of NOR flash EEPROM cells under CHISEL programming operation - impact of technological parameters and scaling | NAIR, DR; SHUKURI, S; MAHAPATRA, S |
| 2008 | Defect generation in p-MOSFETs under negative-bias stress: an experimental perspective | MAHAPATRA, S; ALAM, MA |
| 2003 | A detailed experimental investigation of impact ionization in n-channel metal-oxide-semiconductor field-effect-transistors at very low drain voltages | ANIL, KG; MAHAPATRA, S; EISELE, I |
| 2007 | Development of a 3D simulator for metal Nanocrystal (NC) flash memories under NAND operation | NAINANI, A; PALIT, S; SINGH, PK; GANGULY, U; KRISHNA, N; VASI, J; MAHAPATRA, S |
| 2008 | Development of an ultrafast on-the-fly I DLIN technique to study NBTI in plasma and thermal oxynitride p-MOSFETs | MAHETA, VD; NARESH KUMAR, E; PURAWAT, S; OLSEN, C; AHMED, K; MAHAPATRA, S |
| 2000 | Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs | MAHAPATRA, S; PARIKH, CD; RAMGOPAL RAO, V; VISWANATHAN, CR; VASI, J |
| 2002 | Device scaling effects on substrate enhanced degradation in MOS transistors | MOHAPATRA, NR; MAHAPATRA, S; RAO, VR |
| 1999 | A direct charge pumping technique for spatial profiling of hot-carrier induced interface and oxide traps in MOSFETs | MAHAPATRA, S; PARIKH, CD; VASI, J; RAMGOPAL RAO, V; VISWANATHAN, CR |
| 2000 | Drain bias dependence of gate oxide reliability in conventional and asymmetrical channel MOSFETs in the low voltage regime | ANIL, KG; MAHAPATRA, S; EISELE, I; RAMGOPAL RAO, V; VASI, J |
| 2004 | Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parameters | MAHAPATRA, S; NAIR, DR; SHUKURI, S; BUDE, JD |
| 2007 | Dual-bit/cell SONOS flash EEPROMs: impact of channel engineering on programming speed and bit coupling effect | DATTA, A; BHARATH KUMAR, P; MAHAPATRA, S |
| 2009 | Dual layer Pt metal nanocrystal flash for multi-level-cell NAND application | SINGH, PK; BISHT, G; MAHAPATRA, S; HOFMANN, R; SINGH, K |
| 2008 | The effect of band gap engineering of the nitride storage node on performance and reliability of charge trap flash | SANDHYA, C; GANGULY, U; SINGH, KK; OLSEN, C; SEUTTER, SM; CONTI, G; AHMED, K; KRISHNA, N; VASI, J; MAHAPATRA, S |
| 2003 | The effect of CHE and CHISEL programming operation on drain disturb in flash EEPROMs | NAIR, DR; MOHAPATRA, NR; MAHAPATRA, S; SHUKURI, S; BUDE, JD |
| 2004 | Effect of P/E cycling on drain disturb in flash EEPROMs under CHE and CHISEL operation | MAHAPATRA, S; NAIR, DR; MOHAPATRA, NR; SHUKURI, S; BUDE, JD |
| 2003 | Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs | MOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V; SHUKURI, S; BUDE, JD |
| 2009 | Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler-Nordheim Tunneling Program/Erase Operation | SANDHYA, C; GANGULY, U; CHATTAR, N; OLSEN, C; SEUTTER, SM; DATE, L; HUNG, R; VASI, JA; MAHAPATRA, S |
| 1987 | ELECTROLESS GOLD DEPOSITION FOR ELECTRONIC INDUSTRY | GANU, GM; MAHAPATRA, S |
Showing results 22 to 41 of 138
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