DSpace at IIT Bombay >

Browsing by Author MAHAPATRA, S

Jump to: 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
or enter first few letters:   
Sort by: In order: Results/Page Authors/Record:
Showing results 123 to 142 of 146
< previous   next >
Issue DateTitleAuthor(s)
2013Scaled Gate Stacks for Sub-20-nm CMOS Logic Applications Through Integration of Thermal IL and ALD HfOxJOSHI, K; HUNG, S; MUKHOPADHYAY, S; SATO, T; BEVAN, M; RAJAMOHANAN, B; WEI, A; NOORI, A; MCDOUGALL, B; NI, C; LAZIK, C; SAHELI, G; LIU, P; CHU, D; DATE, L; DATTA, S; BRAND, A; SWENBERG, J; MAHAPATRA, S
1991Selective electroless plating-a new technique for GaAs MMICsMAHAPATRA, S; CHOUDHURY, D; BHATGADDE, LG
2005Soft secondary electron programming for floating gate NOR flash EEPROMsBHARATH KUMAR, P; NAIR, DR; MAHAPATRA, S
1999A study of 100 nm channel length asymmetric channel MOSFET by using charge pumpingMAHAPATRA, S; RAO, VR; PARIKH, CD; VASI, J; CHENG, B; WOO, JCS
2011Study of automatic recovery on the metal nanocrystal-based Al(2)O(3)/SiO(2) gate stackCHEN, YN; PEY, KL; GOH, KEJ; LWIN, ZZ; SINGH, P; MAHAPATRA, S
2012Study of charge distribution and charge loss in dual-layer metal-nanocrystal-embedded high-kappa/SiO2 gate stackLWIN, ZZ; PEY, KL; ZHANG, Q; BOSMAN, M; LIU, Q; GAN, CL; SINGH, PK; MAHAPATRA, S
2002The study of damage generation in n-channel MOS transistors operating in the substrate enhanced gate current regimeMOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V
2001Study of degradation in channel initiated secondary electron injection regimeMOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V
2001A study of hot-carrier induced interface-trap profiles in lateral asymmetric channel MOSFETs using a novel charge pumping techniqueMAHAPATRA, S; RAO, VR; VASI, J; CHENG, B; WOO, JCS
2008A study of NBTI in HfSiON/TiN p-MOSFETs using ultra-fast on-the-fly (UF-OTF) I(DLIN) techniqueDEORA, S; MAHAPATRA, S
2010Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) OperationSANDHYA, C; OAK, AB; CHATTAR, N; GANGULY, U; OLSEN, C; SEUTTER, SM; DATE, L; HUNG, R; VASI, J; MAHAPATRA, S
2003Substrate bias effect on cycling induced performance degradation of flash EEPROMsMAHAPATRA, S; SHUKURI, S; BUDE, JD
2012Temperature-dependent relaxation current on single and dual layer Pt metal nanocrystal-based Al2O3/SiO2 gate stackCHEN, YN; GOH, KEJ; WU, X; LWIN, ZZ; SINGH, PK; MAHAPATRA, S; PEY, KL
1976Temperature profile inside active layer of a gunn diodeJANADHANAN, P; MAHAPATRA, S
2010Tri-Level Resistive Switching in Metal-Nanocrystal-Based Al(2)O(3)/SiO(2) Gate StackCHEN, YN; PEY, KL; GOH, KEJ; LWIN, ZZ; SINGH, PK; MAHAPATRA, S
2000ULSI MOS transistors with jet vapour deposited (JVD) silicon nitride for the gate insulatorMAHAPATRA, S; MANJULARANI, KN; RAO, VR; VASI, J
2013Ultrafast AC-DC NBTI Characterization of Deep IL Scaled HKMG p-MOSFETsGOEL, N; NANAWARE, N; MAHAPATRA, S
2013Understanding Process Impact of Hole Traps and NBTI in HKMG p-MOSFETs Using Measurements and Atomistic SimulationsMAHAPATRA, S; DE, S; JOSHI, K; MUKHOPADHYAY, S; PANDEY, RK; MURALI, KVRM
Showing results 123 to 142 of 146
< previous   next >


Valid XHTML 1.0! DSpace Software Copyright © 2002-2010  Duraspace - Feedback