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Browsing by Author MAHAPATRA, S

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Issue DateTitleAuthor(s)
1999A study of 100 nm channel length asymmetric channel MOSFET by using charge pumpingMAHAPATRA, S; RAO, VR; PARIKH, CD; VASI, J; CHENG, B; WOO, JCS
2011Study of automatic recovery on the metal nanocrystal-based Al(2)O(3)/SiO(2) gate stackCHEN, YN; PEY, KL; GOH, KEJ; LWIN, ZZ; SINGH, P; MAHAPATRA, S
2002The study of damage generation in n-channel MOS transistors operating in the substrate enhanced gate current regimeMOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V
2001Study of degradation in channel initiated secondary electron injection regimeMOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V
2001A study of hot-carrier induced interface-trap profiles in lateral asymmetric channel MOSFETs using a novel charge pumping techniqueMAHAPATRA, S; RAO, VR; VASI, J; CHENG, B; WOO, JCS
2008A study of NBTI in HfSiON/TiN p-MOSFETs using ultra-fast on-the-fly (UF-OTF) I(DLIN) techniqueDEORA, S; MAHAPATRA, S
2010Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) OperationSANDHYA, C; OAK, AB; CHATTAR, N; GANGULY, U; OLSEN, C; SEUTTER, SM; DATE, L; HUNG, R; VASI, J; MAHAPATRA, S
2003Substrate bias effect on cycling induced performance degradation of flash EEPROMsMAHAPATRA, S; SHUKURI, S; BUDE, JD
1986SWITCHED REFLECTION PHASE-SHIFTERKORI, MH; MAHAPATRA, S
1976Temperature profile inside active layer of a gunn diodeJANADHANAN, P; MAHAPATRA, S
2010Tri-Level Resistive Switching in Metal-Nanocrystal-Based Al(2)O(3)/SiO(2) Gate StackCHEN, YN; PEY, KL; GOH, KEJ; LWIN, ZZ; SINGH, PK; MAHAPATRA, S
2000ULSI MOS transistors with jet vapour deposited (JVD) silicon nitride for the gate insulatorMAHAPATRA, S; MANJULARANI, KN; RAO, VR; VASI, J
1993USEFUL PATH-INDEPENDENT INTEGRALS ASSOCIATED WITH TEM-MODE TRANSMISSION-LINES AND A PROCEDURE FOR COMPUTATION OF RATE OF VARIATION OF CAPACITANCE WITH A CROSS-SECTIONAL DIMENSIONPATIL, KD; MAITI, SK; MAHAPATRA, S
2005Use of shared buffering and wavelength conversion for contention resolution in an optical packet switch architectureDEBNATH, S; MAHAPATRA, S; GANGOPADHYAY, R
2006Using soft secondary electron programming to reduce drain disturb in floating-gate nor flash EEPROMsMAHAPATRA, S; BHARATH KUMAR, P; NAIR, DR
1989VERY LARGE-SCALE INTEGRATED CMOS BUFFER DESIGNRAYAPATI, VN; MAHAPATRA, S
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