Browsing by Author MAHAPATRA, S

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Issue DateTitleAuthor(s)
1990PERFORMANCE EVALUATION OF 2 PASSIVE MMIC COMPONENTSCHOUDHURY, D; MAHAPATRA, S
2001Performance optimization of 60 nm channel length vertical MOSFETs using channel engineeringSHRIVASTAV, G; MAHAPATRA, S; RAMGOPAL RAO, V; VASI, J
2013A Physical and SPICE Mobility Degradation Analysis for NBTICHAUDHARY, A; MAHAPATRA, S
2007Physical mechanism and gate insulator material dependence of generation and recovery of negative-bias temperature instability in p-MOSFETsVARGHESE, D; GUPTA, G; LAKKIMSETTI, LM; SAHA, D; AHMED, K; NOURI, F; MAHAPATRA, S
1991PIPE ENCLOSED MICROSTRIP TRANSMISSION-LINEPATIL, KB; MAITI, SK; MAHAPATRA, S
1988POWER REDUCTION METHODS FOR NMOS DYNAMIC RANDOM-ACCESS MEMORIESNAIDU, RV; MAHAPATRA, S
2002A predictive reliability model for PMOS bias temperature degradationMAHAPATRA, S; ALAM, MA
2009Recent advances in charge trap flash memoriesSANDHYA, C; SINGH, PK; GUPTA, S; ROHRA, H; SHIVATHEJA, M; GANGULY, U; HOFMANN, R; MUKHOPADHYAY, G; MAHAPATRA, S; VASI, J
2007Recent issues in negative-bias temperature instability: Initial degradation, field dependence of interface trap generation, hole trapping effects, and relaxationISLAM, AE; KUFLUOGLU, H; VARGHESE, D; MAHAPATRA, S; ALAM, MA
2009Reliability of single and dual layer Pt Nanocrystal devices for NAND flash applications : a 2-region model for endurance defect generationSINGH, PK; BISHT, G; SIVATHEJA, M; SANDHYA, C; MUKHOPADHYAY, G; MAHAPATRA, S; HOFMANN, R; SINGH, K; KRISHNA, N
2000Reliability studies on sub 100 nm SOI-MNSFETsMAHAPATRA, S; RAMGOPAL RAO, V; VASI, J; CHENG, B; WOO, JCS
2006Role of anode hole injection and valence band hole tunneling on interface trap generation during hot carrier injection stressMAHAPATRA, S; SAHA, D; VARGHESE, D
2000Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel MOSFETsANIL, KG; MAHAPATRA, S; EISELE, I
1992S-BAND MEDIUM-POWER MESFET AMPLIFIER WITH HIGH-STABILITYSAMUEL, M; NAWARANGE, A; MAHAPATRA, S
2013Scaled Gate Stacks for Sub-20-nm CMOS Logic Applications Through Integration of Thermal IL and ALD HfOxJOSHI, K; HUNG, S; MUKHOPADHYAY, S; SATO, T; BEVAN, M; RAJAMOHANAN, B; WEI, A; NOORI, A; MCDOUGALL, B; NI, C; LAZIK, C; SAHELI, G; LIU, P; CHU, D; DATE, L; DATTA, S; BRAND, A; SWENBERG, J; MAHAPATRA, S
1991Selective electroless plating-a new technique for GaAs MMICsMAHAPATRA, S; CHOUDHURY, D; BHATGADDE, LG
2005Soft secondary electron programming for floating gate NOR flash EEPROMsBHARATH KUMAR, P; NAIR, DR; MAHAPATRA, S
1979STABILIZATION OF SENSITIZER USED IN THE ELECTROLESS DEPOSITION OF COPPER ON CERAMIC MATERIALSBHATGADDE, LG; MAHAPATRA, S
1999A study of 100 nm channel length asymmetric channel MOSFET by using charge pumpingMAHAPATRA, S; RAO, VR; PARIKH, CD; VASI, J; CHENG, B; WOO, JCS
2011Study of automatic recovery on the metal nanocrystal-based Al(2)O(3)/SiO(2) gate stackCHEN, YN; PEY, KL; GOH, KEJ; LWIN, ZZ; SINGH, P; MAHAPATRA, S