|
|
DSpace at IIT Bombay >
Browsing by Author MAHAPATRA, S
Showing results 116 to 135 of 138
| Issue Date | Title | Author(s) | | 2000 | Reliability studies on sub 100 nm SOI-MNSFETs | MAHAPATRA, S; RAMGOPAL RAO, V; VASI, J; CHENG, B; WOO, JCS |
| 2006 | Role of anode hole injection and valence band hole tunneling on interface trap generation during hot carrier injection stress | MAHAPATRA, S; SAHA, D; VARGHESE, D |
| 2000 | Role of inversion layer quantization on sub-bandgap impact ionization in deep-sub-micron n-channel MOSFETs | ANIL, KG; MAHAPATRA, S; EISELE, I |
| 1992 | S-BAND MEDIUM-POWER MESFET AMPLIFIER WITH HIGH-STABILITY | SAMUEL, M; NAWARANGE, A; MAHAPATRA, S |
| 1991 | Selective electroless plating-a new technique for GaAs MMICs | MAHAPATRA, S; CHOUDHURY, D; BHATGADDE, LG |
| 2005 | Soft secondary electron programming for floating gate NOR flash EEPROMs | BHARATH KUMAR, P; NAIR, DR; MAHAPATRA, S |
| 1979 | STABILIZATION OF SENSITIZER USED IN THE ELECTROLESS DEPOSITION OF COPPER ON CERAMIC MATERIALS | BHATGADDE, LG; MAHAPATRA, S |
| 1999 | A study of 100 nm channel length asymmetric channel MOSFET by using charge pumping | MAHAPATRA, S; RAO, VR; PARIKH, CD; VASI, J; CHENG, B; WOO, JCS |
| 2011 | Study of automatic recovery on the metal nanocrystal-based Al(2)O(3)/SiO(2) gate stack | CHEN, YN; PEY, KL; GOH, KEJ; LWIN, ZZ; SINGH, P; MAHAPATRA, S |
| 2002 | The study of damage generation in n-channel MOS transistors operating in the substrate enhanced gate current regime | MOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V |
| 2001 | Study of degradation in channel initiated secondary electron injection regime | MOHAPATRA, NR; MAHAPATRA, S; RAMGOPAL RAO, V |
| 2001 | A study of hot-carrier induced interface-trap profiles in lateral asymmetric channel MOSFETs using a novel charge pumping technique | MAHAPATRA, S; RAO, VR; VASI, J; CHENG, B; WOO, JCS |
| 2008 | A study of NBTI in HfSiON/TiN p-MOSFETs using ultra-fast on-the-fly (UF-OTF) I(DLIN) technique | DEORA, S; MAHAPATRA, S |
| 2010 | Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation | SANDHYA, C; OAK, AB; CHATTAR, N; GANGULY, U; OLSEN, C; SEUTTER, SM; DATE, L; HUNG, R; VASI, J; MAHAPATRA, S |
| 2003 | Substrate bias effect on cycling induced performance degradation of flash EEPROMs | MAHAPATRA, S; SHUKURI, S; BUDE, JD |
| 1986 | SWITCHED REFLECTION PHASE-SHIFTER | KORI, MH; MAHAPATRA, S |
| 1976 | Temperature profile inside active layer of a gunn diode | JANADHANAN, P; MAHAPATRA, S |
| 2010 | Tri-Level Resistive Switching in Metal-Nanocrystal-Based Al(2)O(3)/SiO(2) Gate Stack | CHEN, YN; PEY, KL; GOH, KEJ; LWIN, ZZ; SINGH, PK; MAHAPATRA, S |
| 2000 | ULSI MOS transistors with jet vapour deposited (JVD) silicon nitride for the gate insulator | MAHAPATRA, S; MANJULARANI, KN; RAO, VR; VASI, J |
| 1993 | USEFUL PATH-INDEPENDENT INTEGRALS ASSOCIATED WITH TEM-MODE TRANSMISSION-LINES AND A PROCEDURE FOR COMPUTATION OF RATE OF VARIATION OF CAPACITANCE WITH A CROSS-SECTIONAL DIMENSION | PATIL, KD; MAITI, SK; MAHAPATRA, S |
Showing results 116 to 135 of 138
|
