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Browsing by Author DESAI, MP

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Issue DateTitleAuthor(s)
2004A novel technique towards eliminating the global clock in VLSI circuitsHAZARI, G; DESAI, MP; GUPTA, A; CHAKRABORTY, SUPRATIK
2004On buffering schemes for long multi-layer netsPRASAD, V; DESAI, MP
2001An on-chip coupling capacitance measurement techniqueNAIR, PA; GUPTA, A; DESAI, MP
2005On range matrices and wireless networks in d dimensionsDESAI, MP; MANJUNATH, D
2002On the connectivity in finite ad hoc networksDESAI, MP; MANJUNATH, D
2007On the impact of address space assignment on performance in systems-on-chipHAZARI, G; DESAI, MP; KASTURE, H
2000Orthogonal partitioning and gated clock architecture for low power realization of FSMsSHELAR, RUPESH S; NARAYANAN, H; DESAI, MP
2007Parallelization of DC analysis through multiport decompositionTRIVEDI, GAURAV; DESAI, MP; NARAYANAN, H
2003The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular functionDESAI, MP; NARAYANAN, H; PATKAR, SB
2003Reconfigurable finite-state machine based IP lookup engine for high-speed routerDESAI, MP; GUPTA, R; KARANDIKAR, ABHAY; SAXENA, K; SAMANT, V
2002Silicon film thickness considerations in SOI-DTMOSDESAI, MP; SIVARAM, P; ANAND, B
2004Silicon film thickness optimization for SOI-DTMOS from circuit performance considerationsDESAI, MP; ANAND, B; RAMGOPAL RAO, V
1999Some results characterizing the finite time behaviour of the simulated annealing algorithmDESAI, MP
1999A state assignment scheme targeting performance and areaGUPTA, BNVM; NARAYANAN, H; DESAI, MP
2001Sub-100 nm CMOS circuit performance with high-K gate dielectricsMOHAPATRA, NR; DUTTA, A; SRIDHAR, G; DESAI, MP; RAO, VR
2005Variance reduction in Monte Carlo capacitance extractionBATTERYWALA, SH; DESAI, MP
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