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Browsing by Author DESAI, MP
Showing results 18 to 35 of 35
Issue Date  Title  Author(s)  2009  Learning based address mapping for improving the performance of memory subsystems  KUMAR, P; DESAI, MP 
2003  Modeling of parasitic capacitances in deep submicrometer conventional and highK dielectric MOS transistors  MOHAPATRA, NR; DESAI, MP; NARENDRA, SG; RAO, VR 
2004  A novel technique towards eliminating the global clock in VLSI circuits  HAZARI, G; DESAI, MP; GUPTA, A; CHAKRABORTY, SUPRATIK 
2004  On buffering schemes for long multilayer nets  PRASAD, V; DESAI, MP 
2001  An onchip coupling capacitance measurement technique  NAIR, PA; GUPTA, A; DESAI, MP 
2005  On range matrices and wireless networks in d dimensions  DESAI, MP; MANJUNATH, D 
2002  On the connectivity in finite ad hoc networks  DESAI, MP; MANJUNATH, D 
2007  On the impact of address space assignment on performance in systemsonchip  HAZARI, G; DESAI, MP; KASTURE, H 
2000  Orthogonal partitioning and gated clock architecture for low power realization of FSMs  SHELAR, RUPESH S; NARAYANAN, H; DESAI, MP 
2007  Parallelization of DC analysis through multiport decomposition  TRIVEDI, GAURAV; DESAI, MP; NARAYANAN, H 
2003  The realization of finite state machines by decomposition and the principal lattice of partitions of a submodular function  DESAI, MP; NARAYANAN, H; PATKAR, SB 
2003  Reconfigurable finitestate machine based IP lookup engine for highspeed router  DESAI, MP; GUPTA, R; KARANDIKAR, ABHAY; SAXENA, K; SAMANT, V 
2002  Silicon film thickness considerations in SOIDTMOS  DESAI, MP; SIVARAM, P; ANAND, B 
2004  Silicon film thickness optimization for SOIDTMOS from circuit performance considerations  DESAI, MP; ANAND, B; RAMGOPAL RAO, V 
1999  Some results characterizing the finite time behaviour of the simulated annealing algorithm  DESAI, MP 
1999  A state assignment scheme targeting performance and area  GUPTA, BNVM; NARAYANAN, H; DESAI, MP 
2001  Sub100 nm CMOS circuit performance with highK gate dielectrics  MOHAPATRA, NR; DUTTA, A; SRIDHAR, G; DESAI, MP; RAO, VR 
2005  Variance reduction in Monte Carlo capacitance extraction  BATTERYWALA, SH; DESAI, MP 
Showing results 18 to 35 of 35
