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DSpace at IIT Bombay >
Browsing by Author DESAI, MP
Showing results 3 to 22 of 35
| Issue Date | Title | Author(s) | | 2007 | Circuit performance improvement using PDSOI-DTMOS devices with a novel optimal sizing scheme considering body parasitics | ANAND, B; RAO, VR; DESAI, MP |
| 1999 | Decomposition of finite state machines for area, delay minimization | SHELAR, RUPESH S; DESAI, MP; NARAYANAN, H |
| 2003 | Detailed analysis of FIBL in MOS transistors with high-k gate dielectrics | MOHAPATRA, NR; DESAI, MP; RAMGOPAL RAO, V |
| 2004 | A distributed and pipelined controller for a modular and scalable hardware emulator | MITTAL, ADITYA; DESAI, MP |
| 2000 | Dynamic threshold voltage MOSFETs for future low power sub 1V CMOS applications | SURYAGANDH, SS; ANAND, B; DESAI, MP; RAO, VR |
| 2001 | Effect of fringing capacitances in sub 100 nm MOSFETs with high-K gate dielectrics | MOHAPATRA, NR; DUTTA, A; DESAI, MP; RAMGOPAL RAO, V |
| 2002 | The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance | DESAI, MP; MOHAPATRA, NR; NARENDRA, SG; RAMGOPAL RAO, V |
| 2004 | The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance | DESAI, MP; NARASIMHULU, K; NARENDRA, SG; RAMGOPAL RAO, V |
| 2002 | Effect of technology scaling on MOS transistor performance with high-K gate dielectrics | MOHAPATRA, NR; DESAI, MP; NARENDRA, SG; RAO, VR |
| 2005 | Fast DC analysis and its application to combinatorial optimization problems | TRIVEDI, G; DESAI, MP; NARAYANAN, H |
| 2006 | Fast DC analysis and its application to combinatorial optimization problems | TRIVEDI, GAURAV; DESAI, MP; NARAYANAN, H |
| 1997 | Finite-time behavior of slowly cooled annealing chains | DESAI, MP; RAO, VB |
| 2002 | Impact of technology scaling on metastability performance of CMOS synchronizing latches | BAGHINI, MS; DESAI, MP |
| 2000 | Inductance characterization of small interconnects using test-signal method | SHAH, JT; DESAI, MP; SANYAL, S |
| 2003 | Interconnect delay minimization using a novel pre-mid-post buffer strategy | PRASAD, V; DESAI, MP |
| 2009 | Learning based address mapping for improving the performance of memory subsystems | KUMAR, P; DESAI, MP |
| 2003 | Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors | MOHAPATRA, NR; DESAI, MP; NARENDRA, SG; RAO, VR |
| 2004 | A novel technique towards eliminating the global clock in VLSI circuits | HAZARI, G; DESAI, MP; GUPTA, A; CHAKRABORTY, SUPRATIK |
| 2004 | On buffering schemes for long multi-layer nets | PRASAD, V; DESAI, MP |
| 2001 | An on-chip coupling capacitance measurement technique | NAIR, PA; GUPTA, A; DESAI, MP |
Showing results 3 to 22 of 35
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