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Browsing by Author DESAI, MP

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Issue DateTitleAuthor(s)
2007Circuit performance improvement using PDSOI-DTMOS devices with a novel optimal sizing scheme considering body parasiticsANAND, B; RAO, VR; DESAI, MP
1999Decomposition of finite state machines for area, delay minimizationSHELAR, RUPESH S; DESAI, MP; NARAYANAN, H
2003Detailed analysis of FIBL in MOS transistors with high-k gate dielectricsMOHAPATRA, NR; DESAI, MP; RAMGOPAL RAO, V
2004A distributed and pipelined controller for a modular and scalable hardware emulatorMITTAL, ADITYA; DESAI, MP
2000Dynamic threshold voltage MOSFETs for future low power sub 1V CMOS applicationsSURYAGANDH, SS; ANAND, B; DESAI, MP; RAO, VR
2001Effect of fringing capacitances in sub 100 nm MOSFETs with high-K gate dielectricsMOHAPATRA, NR; DUTTA, A; DESAI, MP; RAMGOPAL RAO, V
2002The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performanceDESAI, MP; MOHAPATRA, NR; NARENDRA, SG; RAMGOPAL RAO, V
2004The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performanceDESAI, MP; NARASIMHULU, K; NARENDRA, SG; RAMGOPAL RAO, V
2002Effect of technology scaling on MOS transistor performance with high-K gate dielectricsMOHAPATRA, NR; DESAI, MP; NARENDRA, SG; RAO, VR
2005Fast DC analysis and its application to combinatorial optimization problemsTRIVEDI, G; DESAI, MP; NARAYANAN, H
2006Fast DC analysis and its application to combinatorial optimization problemsTRIVEDI, GAURAV; DESAI, MP; NARAYANAN, H
1997Finite-time behavior of slowly cooled annealing chainsDESAI, MP; RAO, VB
2002Impact of technology scaling on metastability performance of CMOS synchronizing latchesBAGHINI, MS; DESAI, MP
2000Inductance characterization of small interconnects using test-signal methodSHAH, JT; DESAI, MP; SANYAL, S
2003Interconnect delay minimization using a novel pre-mid-post buffer strategyPRASAD, V; DESAI, MP
2009Learning based address mapping for improving the performance of memory subsystemsKUMAR, P; DESAI, MP
2003Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistorsMOHAPATRA, NR; DESAI, MP; NARENDRA, SG; RAO, VR
2004A novel technique towards eliminating the global clock in VLSI circuitsHAZARI, G; DESAI, MP; GUPTA, A; CHAKRABORTY, SUPRATIK
2004On buffering schemes for long multi-layer netsPRASAD, V; DESAI, MP
2001An on-chip coupling capacitance measurement techniqueNAIR, PA; GUPTA, A; DESAI, MP
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